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C9870G high performance pentium? 4 clock synthesizer cypress semiconductor corporation http://www.cypress.com document#: 38-07108 rev. *a 12/26/2002 page 1 of 25 a pproved product product features ? supports pentium ? 4 type cpus ? 3.3 volt power supply ? 10 copies of pci clocks ? 3 differential cpu clocks ? smbus support with read-back capabilities ? spread spectrum emi reduction ? dial-a-frequency? features ? dial-a-db? features ? 56 pin ssop and tssop package frequency table s2 s1 s0 cpu (0:2) 3v66 66buff(0:2)/ 3v66(0:4) 66in/ 3v66-5 pci_f pci ref usb/ dot 1 0 0 66m 66m 66in 66mhz clock input 66in/2 14.318m 48m 1 0 1 100m 66m 66in 66mhz clock input 66in/2 14.318m 48m 1 1 0 200m 66m 66in 66mhz clock input 66in/2 14.318m 48m 1 1 1 133m 66m 66in 66mhz clock input 66in/2 14.318m 48m 0 0 0 66m 66m 66m 66m 33 m 14.318m 48m 0 0 1 100m 66m 66m 66m 33 m 14.318m 48m 0 1 0 200m 66m 66m 66m 33 m 14.318m 48m 0 1 1 133m 66m 66m 66m 33 m 14.318m 48m m 0 0 hi-z hi-z hi-z hi-z hi-z hi-z hi-z m 0 1 tclk/2 tclk/4 tclk/4 tclk/4 tclk/8 tclk tclk/2 m 1 0 150m 50m 50m 50m 25m 14.318m 48m m 1 1 166.6m 55.5m 55.5m 55.5m 27.7m 14.318m 48m note: tclk is a test clock over driven on the xtal_in input during test mode. m= driven to a level between 1.0 and 1.8 volts if the s2 pin is at a m level during power up, a 0 state will be latched into the devices internal state register. block diagram pin configuration vdd xin xout vss pcif0 pcif1 pcif2 vdd vss pci0 pci1 pci2 pci3 vdd vss pci4 pci5 pci6 vdd vss 66b0/3v66_2 66b1/3v66_3 66b2/3v66_4 66in/3v66_5 pd# vdda vssa vtt_pg# ref s1 s0 cpu_stp# cpu0 cpu/0 vdd cpu1 cpu/1 vss vdd cpu2 cpu/2 mult0 iref vssiref s2 48musb 48mdot vdd vss 3v66_1/vch pci_stp# 3v66_0 vdd vss sclk sdata 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 C9870G pll1 pll2 /2 wd logic power up logic xin xout cpu_stp# iref vssiref s(0:2) mult0 vtt_pg# pci_stp# pd# sdata sclk vdda 66b[0:2]/3v66[2:4] 48m dot 48m usb pci_f(0:2) pci(0:6) 3v66_1/vch 3v66_0 cpu/(0:2) cpu(0:2) ref 66in/3v66-5 i2c logic
C9870G high performance pentium? 4 clock synthesizer cypress semiconductor corporation http://www.cypress.com document#: 38-07108 rev. *a 12/26/2002 page 2 of 25 a pproved product pin description pin name pwr i/o description 2 xin i oscillator buffer input. connect to a crystal or to an external clock. 3 xout vdd o oscillator buffer output. connect to a crystal. do not connect when an external clock is applied at xin. 52, 51, 49, 48, 45, 44 cpu, cpu/ (0:2) vdd o differential host output clock pairs. see the frequency table on page one of this data sheet for frequencies and functionality. 10, 11, 12, 13, 16, 17, 18 pci(0:6) vddp o pci clock outputs. are synchronous to 66in or 3v66 clock. see frequency table on page one of this data sheet. 5, 6, 7 pcif (0:2) vdd o 33mhz pci clocks, which are 2 copies of 66in or 3v66 clocks, may be free running (not stopped when pci_stp# is asserted low) or may be stoppable depending on the programming of smbus register byte3, bits (3:5). 56 ref vdd o buffered output copy of the device?s xin clock. 42 iref vdd i current reference programming input for cpu buffers. a resistor is connected between this pin and vssiref. see cpu clock current select table in page 18 of this data sheet. 28 vtt_pg# vdd i qualifying input that latches s (0:2) and mult0. when this input is at a logic low, the s (0:2) and mult0 are latched 39 48musb vdd48 o fixed 48mhz usb clock outputs. 38 48mdot vdd48 o fixed 48mhz dot clock outputs. 33 3v66_0 vdd o 3.3 volt 66 mhz fixed frequency clock. 35 3v66_1/vch vdd o 3.3 volt clock selectable with smbus byte0, bit5, when byte5, bit5. when byte 0 bit 5 is at a logic 1, then this pin is a 48m output clock. when byte0, bit5 is a logic 0, then this is a 66m output clock (default). 25 pd# vdd i pu this pin is a power down mode pin. a logic low level causes the device to enter a power down state. all internal logic is turned off except for the smbus logic. all output buffers are stopped. see the power down section of this data sheet. 43 mult0 i pu programming input selection for cpu clock current multiplier. see cpu clock current select function table. 55, 54 s(0,1) i i frequency select inputs. see frequency table on page 1. 29 sdata i i serial data input. conforms to the smbus specification of a slave receive/transmit device. it is an input when receiving data. it is an open drain output when acknowledging or transmitting data. see application note an-0022 30 sclk i i serial clock input. conforms to the smbus specification. see application note an-0022. 40 s2 vdd i t frequency select input. see frequency table on page 1. this is a tri level input that is driven high, low or driven to an intermediate level. 34 pci_stp# vdd i pu pci clock disable input. when asserted low, pci (0:6) clocks are synchronously disabled in a low state. this pin does not effect pcif (0:2) clocks? outputs if they are programmed to be pcif clocks via the device?s smbus interface.
C9870G high performance pentium? 4 clock synthesizer cypress semiconductor corporation http://www.cypress.com document#: 38-07108 rev. *a 12/26/2002 page 3 of 25 a pproved product pin description (cont.) pin name pwr i/o description 53 cpu_stp# vdd i pu cpu clock disable input. when asserted low, cpu (0:2) clocks are synchronously disabled in a high state and cpu/(0:2) clocks are synchronously disabled in a low state. 24 66in/3v66_5 vdd i/o input connection for 66clk(0:2) output clock buffers if s2 = 1, or output clock for fixed 66 mhz clock if s2=0. see table on page 1 21, 22, 23 66b(0:2)/ 3v66(2:4) vdd o 3.3 volt clock outputs. these clocks are buffered copies of the 66in clock or fixed at 66 mhz. see table on page 1 1, 8, 14, 19, 32, 37, 46, 50 vdd pwr 3.3v power supply 4, 9, 15, 20, 27, 31, 36, 47 vss pwr common ground 41 vssiref pwr current reference programming input for cpu buffers. a resistor is connected between this pin and iref. see cpu clock current select table in page 18 of this data sheet. this pin should also be returned to device vss. 26 vdda - pwr analog power input. used for pll and internal analog circuits. is also specifically used to detect and determine when power is at an acceptable level to enable the device to operate. pu = internal pull-up. pd = internal pull-down. t = tri level logic input with valid logic voltages of low=<0.8v, t=1.0-1.8v an d high=>2.0v 2-wire smbus control interface the 2-wire control interface implements a read/write slave only interface according to smbus specification. (see application note an-0022). the device will accept data written to the d2 address and data may read back from address d3. it will not respond to any other addresses, and previously set control registers are retained as long as power in maintained on the device. serial control registers following the acknowledge of the address byte, two additional bytes must be sent: 1) ? command code ? byte, and 2) ? byte count ? byte. although the data (bits) in the command is considered ?don?t care?; it must be sent and will be acknowledged. after the command code and the byte count have been acknowledged, the sequence (byte 0, byte 1, and byte 2) described below will be valid and acknowledged. note: the pin# column lists the relevant pin number where applicable. the @pup column gives the default state at power up.
C9870G high performance pentium? 4 clock synthesizer cypress semiconductor corporation http://www.cypress.com document#: 38-07108 rev. *a 12/26/2002 page 4 of 25 a pproved product serial control registers (cont.) byte 0: cpu clock register bit @pup pin# description 7 0 - spread spectrum enable 0 = spread off, 1 = spread on this is a read and write control bit. 6 0 - reserved 5 0 35 3v66_1/vch frequency select 0 = 66m selected, 1 = 48m selected this is a read and write control bit. 4 pin 53 44,45,48,49, 51,52 cpu_stp#. reflects the current value of the external cpu_stp# (pin 53) this bit is read only. 3 pin 34 10,11,12,13, 16,17,18 reflects the current value of the internal pci_stp# function when read. internally pci_stp# is a logical and function of the internal smbus register bit and the external pci_stp# pin. 2 pin 40 - frequency select bit 2. reflects the value of sel2 (pin 40). this bit is read only. 1 pin 55 - frequency select bit 1. reflects the value of sel1 (pin 55). this bit is read only. 0 pin 54 - frequency select bit 0. reflects the value of sel0 (pin 54). this bit is read only. byte 1: cpu clock register bit @pup pin# description 7 pin 43 - mult0 (pin 43) value. this bit is read only. 6 0 - reserved 5 0 44,45 controls cpu2 functionality when cpu_stp# is asserted low 1 = free running, 0 = stopped low with cpu_stp# asserted low this is a read and write control bit. 4 0 48,49 controls cpu1 functionality when cpu_stp# is asserted low 1 = free running, 0 = stopped low with cpu_stp# asserted low this is a read and write control bit. 3 0 51,52 controls cpu0 functionality when cpu_stp# is asserted low 1 = free running, 0 = stopped low with cpu_stp# asserted low this is a read and write control bit. 2 1 44,45 cpu2 output control, 1 = enabled, 0 = disable high and cpu/2 disables low this is a read and write control bit. 1 1 48,49 cpu1 output control, 1 = enabled, 0 = disable high and cpu/1 disables low this is a read and write control bit. 0 1 51,52 cpu0 output control, 1 = enabled, 0 = disable high and cpu/0 disables low this is a read and write control bit. byte 2: pci clock control register (all bits are read and write functional) bit @pup pin# description 7 0 - reserved 6 1 18 pci6 output control 1 = enabled, 0 = forced low 5 1 17 pci5 output control 1 = enabled, 0 = forced low 4 1 16 pci4 output control 1 = enabled, 0 = forced low 3 1 13 pci3 output control 1 = enabled, 0 = forced low 2 1 12 pci2 output control 1 = enabled, 0 = forced low 1 1 11 pci1 output control 1 = enabled, 0 = forced low 0 1 10 pci0 output control 1 = enabled, 0 = forced low byte 3: pci_f clock and 48m control register (all bits are read and write functional) bit @pup pin# description 7 1 38 48mdot output control 1 = enabled, 0 = forced low 6 1 39 48musb output control 1 = enabled, 0 = forced low 5 0 7 pci_stp#, control of pci_f2. 0 = free running, 1 = stopped when pci_stp# is low 4 0 6 pci_stp#, control of pci_f1. 0 = free running, 1 = stopped when pci_stp# is low 3 0 5 pci_stp#, control of pci_f0. 0 = free running, 1 = stopped when pci_stp# is low 2 1 7 pci_f2 output control 1=running, 0=forced low 1 1 6 pci_f1 output control 1= running, 0=forced low 0 1 5 pci_f0 output control 1= running, 0=forced low
C9870G high performance pentium? 4 clock synthesizer cypress semiconductor corporation http://www.cypress.com document#: 38-07108 rev. *a 12/26/2002 page 5 of 25 a pproved product byte 4: drcg control register (all bits are read and write functional) bit @pup pin# description 7 0 - ss2 spread spectrum control bit (0=down spread, 1=center spread) 6 0 - reserved 5 1 33 3v66_0 output enabled 1 = enabled, 0 = disabled 4 1 35 3v66_1/vch output enable 1 = enabled, 0 = disabled 3 1 24 3v66_5 output enable 1 = enabled, 0 = disabled 2 1 23 66b2/3v66_4 output enabled 1 = enabled, 0 = disabled 1 1 22 66b1/3v66_3 output enabled 1 = enabled, 0 = disabled 0 1 21 66b0/3v66_2 output enabled 1 = enabled, 0 = disabled byte 6: silicon signature register (all bits are read only) bit @pup pin# description 70 - 60 - 50 - 40 - 30 - 20 - 11 - 01 - vendor code 011 = imi note: when writing to this register the device will acknowledge the write operation, but the data itself will be ignored. byte 8: dial-a-frequency? control register n (all bits are read and write functional) bit @pup pin# description 70 0n7, msb 60 0n6 50 0n5 40 0n4 30 0n3 20 0n2 10 0n3 0 0 0 n0, lsb 66in to 66m delay control table byte5 bit5 bit4 delay (ns) 0 0 4.29 0 1 4.43 1 0 3.95 (default) 1 1 3.95 byte 5: clock control register (all bits are read and write functional) bit @pup pin# description 7 0 - ss1 spread spectrum control bit 6 1 - ss0 spread spectrum control bit 5 0 - 66in to 66m delay control msb, see table 4 0 - 66in to 66m delay control lsb, see table 3 0 - reserved 2 0 - 48mdot edge rate control. when set to 1, the edge is slowed by 15%. 1 0 - reserved 0 0 - usb edge rate control. when set to 1, the edge is slowed by 15% byte 7: watch dog time stamp register bit @pup pin# description 7 0 - reserved 6 0 - reserved 5 0 - reserved 40 - reserved 3 0 - reserved 2 0 - reserved 1 0 - reserved 0 0 - reserved byte 9: dial-a-frequency? control register r (all bits are read and write functional) bit @pup pin# description 70 -r6 msb 60 -r5 50 -r4 40 -r3 3 0 -r2 2 0 -r1 1 0 - r0, lsb 0 0 - r and n register load gate 0=gate closed (data is latched), 1=gate open (data is loading from smbus registers into r and n)
C9870G high performance pentium? 4 clock synthesizer cypress semiconductor corporation http://www.cypress.com document#: 38-07108 rev. *a 12/26/2002 page 6 of 25 a pproved product dial-a-frequency ? feature smbus dial-a-frequency feature is available in this device via byte8 and byte9. see our app note an-0025 for details on our dial-a-frequency? feature. p is a large value pll constant that depends on the frequency selection achieved through the hardware selectors (s1, s0). p value may be determined from the following table: s(1:0) p 0 0 32005333 0 1 48008000 1 0 96016000 1 1 64010667 table 1 dial-a-db? features smbus dial-a-db? feature is available in this device via byte8 and byte9. see our app note an-0026 for details on the dial-a-db?. spread spectrum clock generation (sscg) spread spectrum is a modulation technique used to minimizing electro-magnetic interference (emi) radiation generated by repetitive digital signals. a clock presents the greatest emi energy at the center frequency it is generating. spread spectrum distributes this energy over a specific and controlled frequency bandwidth therefore causing the average energy at any one point in this band to decrease in value. this technique is achieved by modulating the clock away from its resting frequency by a certain percentage (which also determines the amount of emi reduction). in this device, spread spectrum is enabled by setting specific register bits in the smbus control bytes. see applications note an-0024 for a more in depth description of spread spectrum modulation and see the smbus register section of this data sheet for the exact bit and byte functionally. the following table is a listing of the modes and percentages of spread spectrum modulation that this device incorporates. ss2 ss1 ss0 spread mode spread % 0 0 0 down 0, -1.00 0 0 1 down 0, -1.20 0 1 0 down 0, -0.50 0 1 1 down 0, -1.50 1 0 0 center +0.50, -0.50 1 0 1 center +0.60, -0.60 1 1 0 center +0.25, -0.25 1 1 1 center +0.75, -0.75
C9870G high performance pentium? 4 clock synthesizer cypress semiconductor corporation http://www.cypress.com document#: 38-07108 rev. *a 12/26/2002 page 7 of 25 a pproved product ac parameters 66 mhz 100 mhz 133 mhz 200 mhz symbol parameter min max min max min max min max units notes tdc xin duty cycle 47.5 52.5 47.5 52.5 47.5 52.5 47.5 52.5 % 1, 11, 14 tperiod xin period 69.841 71.0 69.841 71.0 69.841 71.0 69.841 71.0 ns 1, 2, 4, 11 vhigh xin high voltage .7vdd vdd .7vdd vdd .7vdd vdd .7vdd vdd volts vlow xin low voltage 0 .3vdd 0 .3vdd 0 .3vdd 0 .3vdd volts tr / tf xin rise and fall times - 10.0 - 10.0 - 10.0 - 10.0 ns 13 tccj xin cycle to cycle jitter - 500 - 500 - 500 - 500 ps 2, 5, 11 cpu at 0.7 volts timing tskew any cpu to cpu clock skew - 100 - 100 - 100 - 100 ps 2, 5, 17 tccj cpu cycle to cycle jitter - 150 - 150 - 150 150 ps 2, 17, 22 tdc cpu and cpu# duty cycle 45 55 45 55 45 55 45 55 % 5, 17, 22 tperiod cpu and cpu# period 14.85 15.3 9.85 10.2 7.35 7.65 4.85 5.1 ns 5, 17, 22 tr / tf cpu and cpu# rise and fall times 175 700 175 700 175 700 175 700 ps 5, 6, 25 rise.fall matching - 20% - 20% 20% - 20% - 6, 21, 22 deltatr rise time variation - 125 - 125 - 125 125 ps 6, 22 deltatf fall time variation - 125 - 125 - 125 - 125 ps 6, 22 vcross crossing point voltage at 0.7 v swing 280 430 280 430 280 430 280 430 mv 5, 22 cpu at 1.0 volts timing tskew any cpu to any cpu clock skew - 100 - 100 - 100 - 100 ps 2, 5, 17 tccj cpu cycle to cycle jitter - 150 - 150 - 150 150 ps 2, 17 tdc cpu and cpu# duty cycle 45 55 45 55 45 55 45 55 % 5, 17 tperiod cpu and cpu# period 14.85 15.3 9.85 10.2 7.35 7.65 4.85 5.1 ns 5, 17 differential tr / tf cpu and cpu# rise and fall times 175 467 175 467 175 467 175 467 ps 5, 25 se- deltaslew absolute single- ended rise/fall waveform symmetry 325 325 325 325 ps 7, 26 vcross cross point at 1.0 volt swing 510 760 510 760 510 760 510 760 mv 26 tdc 3v66 duty cycle 45 55 45 55 45 55 45 55 % 2, 4 tperiod 3v66 period 15.0 15.3 15.0 15.3 15.0 15.3 15.0 15.3 ns 1, 2, 4 thigh 3v66 high time 4.95 - 4.95 - 4.95 - 4.95 - ns 19 tlow 3v66 low time 4.55 - 4.55 - 4.55 - 4.55 - ns 20 tr / tf 3v66 rise and fall times 0.5 2.0 0.5 2.0 0.5 2.0 0.5 2.0 ns 3 tskew unbuffered 3v66 to 3v66 clock skew - 500 - 500 - 500 - 500 ps 2, 4 tskew buffered 3v66 to 3v66 clock skew - 250 - 250 - 250 - 250 ps 2, 4 tccj drcg cycle to cycle jitter - 250 - 250 - 250 - 250 ps 2, 4
C9870G high performance pentium? 4 clock synthesizer cypress semiconductor corporation http://www.cypress.com document#: 38-07108 rev. *a 12/26/2002 page 8 of 25 a pproved product ac parameters (cont.) 66 mhz 100 mhz 133 mhz 200 mhz symbol parameter min max min max min max min max units notes tdc 66b(0:2) duty cycle 45 55 45 55 45 55 45 55 % 2, 4 tr / tf 66b(0:2) rise and fall times 0.5 2.0 0.5 2.0 0.5 2.0 0.5 2.0 ns 2, 3 tskew any 66b to any 66b skew - 175 - 175 - 175 175 ps 2, 4 tpd 66in to 66b(0:2) propagation delay 2.5 4.5 2.5 4.5 2.5 4.5 2.5 4.5 ns 2, 4 tccj 66b(0:2) cycle to cycle jitter - 100 - 100 - 100 - 100 ps 2, 4, 18 tdc pci_f(0:2) pci (0:6) duty cycle 45 55 45 55 45 55 45 55 % 2, 4 tperiod pci_f(0:2) pci (0:6) period 30.0 - 30.0 - 30.0 - 30 - ns 1, 2, 4 thigh pci_f(0:2) pci (0:6) high time 12.0 - 12.0 - 12.0 - 12.0 - ns 19 tlow pci_f(0:2) pci (0:6) low time 12.0 - 12.0 - 12.0 - 12.0 - ns 20 tr / tf pci_f(0:2) pci (0:6) rise and fall times 0.5 2.0 0.5 2.0 0.5 2.0 0.5 2.0 ns 3 tskew any pci clock to any pci clock skew - 500 - 500 - 500 - 500 ps 2, 4 tccj pci_f(0:2) pci (0:6) cycle to cycle jitter - 250 - 250 - 250 - 250 ps 2, 4 tdc usb48m duty cycle 45 55 45 55 45 55 45 55 % 2, 4 tperiod usb48m period 20.8299 20.8333 20.8299 20.8333 20.8299 20.8333 20.8299 20.8333 ns 2, 4 tr / tf usb48m rise and fall times 1.0 2.0 1.0 2.0 1.0 2.0 1.0 2.10 ns 2, 3 tccj usb48m cycle to cycle jitter - 350 - 350 - 350 - 350 ps 1, 2, 4 tdc dot48 duty cycle 45 55 45 55 45 55 45 55 % 2, 4 tperiod dot48 period 20.837 20.837 20.837 20.837 ns 2, 4 tr / tf dot48 rise and fall times 0.5 1.0 0.5 1.0 0.5 1.0 0.5 1.0 ns 2, 4 tccj dot48cycle to cycle jitter - 350 - 350 - 350 - 350 ps 2, 4
C9870G high performance pentium? 4 clock synthesizer cypress semiconductor corporation http://www.cypress.com document#: 38-07108 rev. *a 12/26/2002 page 9 of 25 a pproved product ac parameters (cont.) 66 mhz 100 mhz 133 mhz 200 mhz symbol parameter min max min max min max min max units notes tdcref duty cycle4555455545554555 % 2, 4 tperiod ref period 69.8413 71.0 69.8413 71.0 69.8413 71.0 69.8413 71.0 ns 2, 4 tr / tf ref rise and fall times 1.0 4.0 1.0 4.0 1.0 4.0 1.0 4.0 ns 2, 3 tccj ref cycle to cycle jitter - 1000 - 1000 - 1000 - 1000 ps 2, 4 tpzl, tpzh output enable delay (all outputs) 1.0 10.0 1.0 10.0 1.0 10.0 1.0 10.0 ns 11 tplz, tpzh output disable delay (all outputs) 1.0 10.0 1.0 10.0 1.0 10.0 1.0 10.0 ns 11 tstable all clock stabilization from power-up -3-3-3-3ms 11 tss stopclock set up time 10.0 - 10.0 - 10.0 - 10.0 - ns 10 tsh stopclock hold time 0-0-0-0-ns 10 tsu oscillator startup time -x-x-x-xms 12 (vdd = vdda = 3.3v 5%, ta = 0 c to +70 c) note 1: this parameter is measured as an average over 1us duration, with a crystal center frequency of 14.31818mhz note 2: all outputs loaded as per table 5 below. note 3: probes are placed on the pins, and measurements are acquired between 0.4v and 2.4v for 3.3v signals (see test and measurement setup section of this data sheet) note 4: probes are placed on the pins, and measurements are acquired at 1.5v for 3.3v signals (see test and measurement setup section o f this data sheet). note 5: this measurement is applicable with spread on or spread off. note 6: measured from vol = 0.175v to voh = 0.525v. note 7: measurements taken from common mode waveforms, measure rise/fall time from 0.41 to 0.86v. rise/fall time matching is defined as ?the instantaneous difference between maximum clk rise (fall) and minimum clk# fall (rise) time, or minimum clk rise (fall) and maxi mum clk# fall (rise) time?. this parameter is designed form waveform symmetry. note 8: the time specified is measured from when all vdd?s reach their supply rail (3.3v) till the frequency output is stable and opera ting within the specifications. note 9: measured from when both sel1 and sel0 are low note 10: cpu_stp# and pci_stp# setup time with respect to any pci_f clock to guarantee that the effected clock will stop or start at the next pci_f clock?s rising edge. note 11: when xin is driven from an external clock source. note 12: when crystal meets minimum 40 ohm device series resistance specification. note 13: measured between 0.2vdd and .7vdd note 14: this is required for the duty cycle on the ref clock out to be as specified. the device will operate reliably with input duty c ycles up to 30/70 but the ref clock duty cycle will not be within data sheet specifications. note 15: vpullup(external)=1.5v, min=(vpullup(external)/2)-150mv, max=(vpullup(external)/2)+150mv note 16: vp = v pull-up (external), vdif specifies the minimum input differential voltage (vtr-vcp) required for switching, where vtr is the true input level and vcp is the compliment input level. note 17: measured at crossing point (vx) or where subtraction of clk-clk# crosses 0 volts. note 18: this figure is additive to any jitter already present when the 66in pin is being used as an input. otherwise a 500 ps jitter f igure is specified. note 19: thigh is measured at 2.4v for non host outputs. note 20: tlow is measured at 0.4v for all outputs. note 21: determined as a fraction of 2*(trise-tfall)/ (trise+tfall). note 22: test load is rta=33.2 ohms, rd=49.9 ohms. note 23: these crossing points refer to only crossing points containing a rising edge of a host output. note 24: this measurement refers to the total variation from the lowest crossing point to the highest, regardless of which edge is cros sing. note 25: measurement taken from differential waveform, from ?0.35v to +0.35v. note 26: measured in absolute voltage, i.e. single-ended measurement.
C9870G high performance pentium? 4 clock synthesizer cypress semiconductor corporation http://www.cypress.com document#: 38-07108 rev. *a 12/26/2002 page 10 of 25 a pproved product maximum lumped capacitive output loads clock max load units pci clocks 30 pf 3v66 (0,1) 30 pf 66b(0:2) 30 pf 48musb clock 20 pf 48mdot 10 pf ref clock 30 pf table 5 maximum ratings1 input voltage relative to vss: vss-0.3v input voltage relative to vddq or avdd: vdd+0.3v storage temperature: -65 c to + 150 c operating temperature: 0 c to +85 c maximum power supply: 3.5v note 1: the voltage on any input or i/o pin cannot exceed the power pin during power-up. power supply sequencing is not required. test and measurement setup for differential cpu output signals the following diagram shows lumped test load configurations for the differential host clock outputs. clk measurement point r ref r ta1 clk clk# mult0 clk measurement point r la1 r d r lb1 r la2 r lb2 r ta2 r tb1 r tb2 c la c lb t pcb t pcb lumped test load configuration component 0.7 volt amplitude value 1.0 volt amplitude value r ta1 , r ta2 33 ? 0 ? r la1 , r la2 49.9 ? t pcb 3? 50 ? z 3? 50 ? z r lb1 , r lb2 63 ? r d 470 ? r tb1 , r tb2 0 ? 33 ? c la , c lb 2pf 2 pf r ref 475 ? w/mult0=1 221 ? w/mult0=0
C9870G high performance pentium? 4 clock synthesizer cypress semiconductor corporation http://www.cypress.com document#: 38-07108 rev. *a 12/26/2002 page 11 of 25 a pproved product test and measurement setup (cont.) for single ended output signals buffer characteristics current mode cpu clock buffer characteristics the current mode output buffer detail and current reference circuit details are contained in the previous table of this data sheet. the following parameters are used to specify output buffer characteristics: 1. output impedance of the current mode buffer circuit - ro (see figure below). 2. minimum and maximum required voltage operation range of the circuit ? vop (see figure below). 3. series resistance in the buffer circuit ? ros (see figure below). 4. current accuracy at given configuration into nominal test load for given configuration. 2.4v 0.4v 3.3v 0v tr tf 1.5v 3.3v signals tdc probe output under test load cap - -
C9870G high performance pentium? 4 clock synthesizer cypress semiconductor corporation http://www.cypress.com document#: 38-07108 rev. *a 12/26/2002 page 12 of 25 a pproved product 1.2v 0v iout iout ros ro vdd3 (3.3v +/- 5%) vout = 1.2v max vout slope ~ 1/r 0 host clock (hcsl) buffer characteristics characteristic minimum maximum ro 3000 ohms (recommended) n/a ros vout n/a 1.2v iout is selectable depending on implementation. the parameters above apply to all configurations. vout is the voltage at the pin of the device. the various output current configurations are shown in the host swing select functions table. for all configurations, the deviation from the expected output current is +/- 7% as shown in the current accuracy table. cpu clock current select function mult0 board target trace/term z reference r, iref ? vdd (3*rr) output current voh @ z 0 50 ohms rr = 221 1%, iref = 5.00ma ioh = 4*iref 1.0v @ 50 1 50 ohms rr = 475 1%, iref = 2.32ma ioh = 6*iref 0.7v @ 50
C9870G high performance pentium? 4 clock synthesizer cypress semiconductor corporation http://www.cypress.com document#: 38-07108 rev. *a 12/26/2002 page 13 of 25 a pproved product group timing relationship and tolerances offset tolerance conditions 3v66 to pci 2.5 ns 1.0 ns 3v66 leads pci (un-buffered mode) usb to dot 48m skew 0.0 ns 1.0 ns 0 degrees phase shift 66b(0:2) to pci offset 2.5 ns 1.0 ns 66b leads pci (buffered mode) usb and dot 48m phase relationship the 48musb and 48mdot clocks are in phase. it is understood that the difference in edge rate will introduce some inherent offset. when 3v66_1/vch clock is configured for vch (48mhz) operation it is also in phase with the usb and dot outputs. usb48m dot48m 48musb and 48mdot phase relationship figure 66in to 66b(0:2) buffered prop delay the 66in to 66b(0:2) output delay is shown below. 66in 66cb0:2) tpd 66in to 66b(0:2) output delay figure the tpd is the prop delay from the input pin (66in) to the output pins (66b[0:2]). the outputs? variation of tpd is described in the ac parameters section of this data sheet. the measurement taken at 1.5 volts.
C9870G high performance pentium? 4 clock synthesizer cypress semiconductor corporation http://www.cypress.com document#: 38-07108 rev. *a 12/26/2002 page 14 of 25 a pproved product 66buf to pci buffered clock skew the following figure shows the difference (skew) between the 3v33(0:5) outputs when the 66m clocks are connected to 66in. this offset is described in the group timing relationship and tolerances section of this data sheet. the measurements were taken at 1.5 volts. 66buf(0:2) pci(0:6) pcif(0:2) 1.5- 3.5ns buffer mode ? 33v66(0:1); 66buf(0:2) phase relationship 3v66 to pci un-buffered clock skew the following figure show the timing relationship between 3v66_(0:5) and pci(0:6) and pcif(0:2) when configured to run in the un-buffered mode. 3v66_(0:5) pci(0:6) pcif(0:2) 1.5- 3.5ns un-buffered mode - 3v66_(0:5) to pci (0:6) and pcif(0:2) phase relationship
C9870G high performance pentium? 4 clock synthesizer cypress semiconductor corporation http://www.cypress.com document#: 38-07108 rev. *a 12/26/2002 page 15 of 25 a pproved product special functions pci_f and ioapic clock outputs the pcif clock outputs are intended to be used, if required, for systems ioapic clock functionality. any 2 of the pci_f clock outputs can be used as ioapic 33mhz clock outputs. they are 3.3v outputs will be divided down via a simple resistive voltage divider to meet specific system ioapic clock voltage requirements. in the event these clocks are not required, then these clocks can be used as general pci clocks or disabled via the assertion of the pci_stp# pin. 3v66_1/vch clock output the 3v66_1/vch pin has a dual functionality, which is selectable via smbus. configured as drcg (66m), smbus byte0, bit 5 = ?0? the default condition for this pin is to power up in a 66m operation. in 66m operation this output is sscg capable and when spreading is turned on, this clock will be modulated. configured as vch (48m), smbus byte0, bit 5 = ?1? in this mode, the output is configured as a 48mhz non-spread spectrum output. this output is phase aligned with the other 48m outputs (usb and dot), to within 1ns pin to pin skew. the switching of 3v66_1/vch into vch mode occurs at system power on. when the smbus bit 5 of byte 0 is programmed from a ?0? to a ?1?, the 3v66_1/vch output may glitch while transitioning to 48m output mode. cpu_stp# clarification the cpu_stp# signal is an active low input used for synchronous stopping and starting the cpu output clocks while the rest of the clock generator continues to function.
C9870G high performance pentium? 4 clock synthesizer cypress semiconductor corporation http://www.cypress.com document#: 38-07108 rev. *a 12/26/2002 page 16 of 25 a pproved product cpu_stp# - assertion (transition from logic ?1? to logic ?0?) when cpu_stp# pin is asserted, all cpu outputs that are set with the smbus configuration to be stoppable via assertion of cpu_stp# will be stopped after being sampled by 2 falling cpu clock edges. the final state of the stopped cpu signals is cpu = high and cpu0# = low. there is no change to the output drive current values during the stopped state. the cpu is driven high with a current value equal to (mult 0 ?select?) x (iref), and the cpu# signal will not be driven. due to external pulldown circuitry cpu# will be low during this stopped state. cpu_stp# cpu cpu# assertion cpu_stp# waveform figure cpu_stp# functionality table cpu_stp# cpu#4 cpu drcg 66clk(0:2) pci_f/pci pci usb/dot 1 normal normal 66m 66input 66input/2 66input/2 48m 0 iref*mult float 66m 66input 66input/2 66input/2 48m cpu_stp# de-assertion (transition from logic ?0? to logic ?1?) the de-assertion of the cpu_stp# signal will cause all cpu outputs that were stopped to resume normal operation in a synchronous manner. synchronous manner meaning that no short or stretched clock pulses will be produces when the clock resumes. the maximum latency from the de-assertion to active outputs is no more than 2 cpu clock cycles.
C9870G high performance pentium? 4 clock synthesizer cypress semiconductor corporation http://www.cypress.com document#: 38-07108 rev. *a 12/26/2002 page 17 of 25 a pproved product pci_stp# clarification the pci_stp# signal is an active low input used for synchronous stopping and starting the pci outputs while the rest of the clock generator continues to function. the setup time for capturing pci_stp# going low is 10 nsec (t setup ). the pci_f (0:2) clocks will not be affected by this pin if their control bits in the smbus register are set to allow them to be free running. pci_stp# pci_f(0:2) 33m pci(0:6) 33m setup t pci_stp# waveform figure pci_stp# - de-assertion (transition from logic ?0? to logic ?1?) the de-assertion of the pci_stp# signal will cause all pci(0:6) and stoppable pci_f(0:2) clocks to resume running in a synchronous manner within 2 pci clock periods after pci_stp# transitions to a high level. note that the pci stop function is controlled by 2 inputs. one is the device pci_stp# pin number 34 and the other is smbus byte 0 bit 3. these 2 inputs to the function are logically anded. if either the external pin or the internal smbus register bit is set low then the stoppable pci clocks will be stopped in a logic low state. reading smbus byte 0 bit 3 will return a 0 value if either of these control bits are set low thereby indicating the devices stoppable pci clocks are not running.
C9870G high performance pentium? 4 clock synthesizer cypress semiconductor corporation http://www.cypress.com document#: 38-07108 rev. *a 12/26/2002 page 18 of 25 a pproved product pd# (power down) clarification the pd# (power down) pin is used to shut off all clocks prior to shutting off power to the device. pd# is an asynchronous active low input. this signal is synchronized internally to the device powering down the clock synthesizer. pd# is an asynchronous function for powering up the system. when pd# is low, all clocks are driven to a low value and held there and the vco and pll?s are also powered down. all clocks are shut down in a synchronous manner so has not to cause glitches while transitioning to the low ?stopped? state. pd# functionality pd# cpu cpu# drcg 66clk (0:2) pci_f/pci pci usb/dot 1 normal normal 66m 66input 66input/2 66input/2 48m 0 iref*2 float low low low low low low pd# - assertion (transition from logic ?l? to logic ?0?)- buffered mode when pd# is sampled low by two consecutive rising edges of the cpu# clock, then on the next high to low transition of pcif, the pcif clock is stopped low. on the next high to low transition of 66buff, the 66buff clock is stopped low. from this time, each clock will stop low on it?s next high to low transition, except the cpu clock. the cpu clocks are held with the cpu clock pin driven high with a value of 2 x iref, and cpu# un-driven. after the last clock has stopped, the rest of the generator will be shut down. 66buff[0..2] pcif pwrdwn# cpu 133mhz cpu# 133mhz 3v66 66in ref 14.318mhz usb 48mhz power down assertion timing waveforms figure ? buffered mode
C9870G high performance pentium? 4 clock synthesizer cypress semiconductor corporation http://www.cypress.com document#: 38-07108 rev. *a 12/26/2002 page 19 of 25 a pproved product pci 33mhz pwrdwn# cpu 133mhz cpu# 133mhz 3v66 ref 14.318mhz usb 48mhz power down assertion timing waveforms figure ? non-buffered mode
C9870G high performance pentium? 4 clock synthesizer cypress semiconductor corporation http://www.cypress.com document#: 38-07108 rev. *a 12/26/2002 page 20 of 25 a pproved product pd# - de-assertion (transition from logic ?0? to logic ?1?) the power-up latency between pd# rising to a valid logic ?1? level and the starting of all clocks is less than 3.0 ms. cpu 133mhz 3v66 cpu# 133mhz ref 14.318mhz usb 48mhz pcif / apic 33mhz 66in 66buff[0,2] pwrdwn# 66buff1 / gmch 100us max <3ms pci 33mhz 30us min power down de-assertion timing waveforms figure
C9870G high performance pentium? 4 clock synthesizer cypress semiconductor corporation http://www.cypress.com document#: 38-07108 rev. *a 12/26/2002 page 21 of 25 a pproved product vtt_pwrgd# timing diagram vid (0:3), sel (0,1) vtt_pwrgd# pwrgd vdd clock gen clock state clock outputs clock vco 0.2-0.3ms delay state 0 state 2 state 3 wait for vtt_gd# sample sels off off on on state 1 (note a) note a: device is not effected, vtt_pwrgd# is ignored. clock generator powerup/run state diagram v t t p w r g d # = l o w delay 0.25ms s1 power off s0 vdda = 2.0v sample inputs (pins 54,55) s2 vdd3.3 = off normal operation s3 enable outputs
C9870G high performance pentium? 4 clock synthesizer cypress semiconductor corporation http://www.cypress.com document#: 38-07108 rev. *a 12/26/2002 page 22 of 25 a pproved product dc characteristics current accuracy conditions configuration load min max iout vdd = nominal (3.30v) m0 = 0 or 1 and rr shown in table nominal test load for given configuration -7% inom + 7% inom iout vdd = 3.30 +/- 5% all combinations of m0 or 1 and rr shown in table nominal test load for given configuration -12% inom + 12% inom note: inom refers to the expected current based on the configuration of the device. dc component parameters (vdd = 3.3v 5%, ta = 0 c to +70 c) characteristic symbol min typ max units conditions dynamic supply current idd3.3v - - 280 ma all frequencies at maximum values, note 1 power down supply current ipd3.3v - - see note 2 ma pd# asserted input pin capacitance cin - - 5 pf output pin capacitance cout - - 6 pf pin inductance lpin - - 7 nh crystal pin capacitance cxtal 30 36 42 pf measured from the xin or xout pin to ground. note1: all outputs loaded as per maximum capacitive load table. note2: absolute value = ((programmed cpu iref) (7)) + 10 ma
C9870G high performance pentium? 4 clock synthesizer cypress semiconductor corporation http://www.cypress.com document#: 38-07108 rev. *a 12/26/2002 page 23 of 25 a pproved product package drawing and dimensions 56 pin ssop outline dimensions inches millimeters symbol min nom max min nom max a 0.095 0.102 0.110 2.41 2.59 2.79 a 1 0.008 0.012 0.016 0.203 0.305 0.406 a2 0.088 - 0.092 2.24 - 2.34 b 0.008 - 0.0135 0.203 - 0.343 c 0.005 - 0.010 0.127 - 0.254 d 0.720 0.725 0.730 18.29 18.42 18.54 e 0.291 0.295 0.299 7.39 7.49 7.60 e 0.025 bsc 0.635 bsc h 0.395 - 0.420 10.03 - 10.67 l 0.020 - 0.040 0.508 - 1.016 a 0o - 8o 0o - 8o 56 pin tssop outline dimensions inches millimeters symbol min nom max min nom max a - - 0.047 - - 1.20 a 1 0.002 - 0.006 0.05 - 0.15 a2 0.031 0.039 0.041 0.80 1.00 1.05 b 0.007 - 0.011 0.17 - 0.27 c 0.004 - 0.008 0.09 - 0.20 d 0.547 0.551 0.555 13.90 14.00 14.10 e 0.236 0.240 0.244 6.00 6.10 6.20 e 0.02 bsc 0.50 bsc h 0.315 0.319 0.323 8.00 8.10 8.20 l 0.018 0.024 0.030 0.45 0.60 0.75 a 0o - 8o 0o - 8o a b e a a 1 a 2 d e h l c
C9870G high performance pentium? 4 clock synthesizer cypress semiconductor corporation http://www.cypress.com document#: 38-07108 rev. *a 12/26/2002 page 24 of 25 a pproved product ordering information part number package type product flow C9870Gy 56 pin ssop commercial, 0 to 85 c C9870Gt 56 pin tssop commercial, 0 to 85 c marking: example: imi c9870 date code, lot # C9870Gy package y = ssop t = tssop revision device number notice cypress semiconductor corporation reserves the right to make changes to its products in order to improve design, performance or reliability. cypress semiconductor corporation assumes no responsibility for the use of its products in life supporting and medical applications where the failure or malfunction of the product could cause failure of the life supporting and medical systems. products are not authorized for use in such applications unless a written approval is requested by the manufacturer and an approval is given in writing by cypress semiconductor corporation for the use of its products in the life supporting and medical applications.
C9870G high performance pentium? 4 clock synthesizer cypress semiconductor corporation http://www.cypress.com document#: 38-07108 rev. *a 12/26/2002 page 25 of 25 a pproved product document title: C9870G high performance pentium? 4 clock synthesizer document number: 38-07108 rev ecn no. issue date orig. of change description of change ** 107512 06/14/01 ndp convert from imi to cypress *a 122786 12/26/02 rbi add power up requirements to maximum ratings information.

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